Field of the Invention: The present invention relates generally to structures for providing interconnections for semiconductor devices. More particularly, it relates to ball grid array (BGA) packages and conductive structures for interconnecting semiconductor devices to the BGA packages.
Semiconductor devices are packaged in many ways. The packaging performs a number of functions, one of the most important being the creation of a connection mechanism between bond pads on a semiconductor die and some type of substrate to which the packaged semiconductor die is mounted.
Packaging memory devices can have a unique set of problems. In memory architectures, it is often advantageous to place the die bond pads down the center of a die, creating a lead over chip (LOC) or board on chip (BOC) configuration. LOC package structures typically employ an etched or stamped lead frame with a slot down the center. The active surface of the die is attached to a bottom surface of the lead frame. Bonding is accomplished by placing bond wires on the bond pads running down the center of the die. The bond wires then extend through the slot in the lead frame and attach to a top surface on the lead frame. An encapsulant is then applied over the die and over a portion of the lead frame to protect the bonding wires. These packages typically come in the form of plastic leaded chip carriers, small outline packages, and thin shrink small outline packages. BOC package structures are similar but typically comprise some type of interposer substrate carrying conductive traces. The active surface of the die is attached to a bottom surface of a structural interposer layer with signal routing on the interposer layer. As with LOC packages, an encapsulant typically protects the bonding pads and bond wires. BOC packages are also available in a variety of package configurations.
BGA packages have become increasingly popular due to the high signal densities available from arranging the package interface signals in an array and work particularly well with BOC package configurations. In one type of BGA product, the interposer is comprised of a resin material, which is adhered to the active surface of a semiconductor die. Solder balls are formed on the resin material. Conductive traces on the resin material connect to the solder balls and to bonding wires connected to bond pads of the semiconductor die. It would be advantageous to incorporate a reinforcing layer in this type of packaging configuration to add stiffness and provide a more substantial substrate without substantially increasing overall size of the package.
As BGA packages migrate toward higher connection densities, such as Fine Pitch Ball Grid Arrays (FBGA) and Extra Fine Pitch Ball Grid Arrays (EFBGA), some additional problems become more severe. The trend toward higher speeds in smaller packages creates both thermal and electrical problems. As semiconductor package size decreases, operating frequencies increase, circuit densities increase, and significant heat is generated, which must be dissipated away from the die as effectively as possible. Heat dissipation is a particular problem with a smaller package where there is less surface area for heat dissipation. These problems of providing structural stiffness and heat dissipation have been addressed in the past. Kinsman et al. in U.S. Pat. No. 6,268,650 and Abram M. Castro in U.S. Pat. No. 6,300,165 each address semiconductor device assemblies providing enhanced thermal performance with added structural stiffness.
However, higher operating frequencies and higher signal frequencies employed in current semiconductor devices also create coupling noise between signals as well as voltage bounce and noise on power and ground voltage references. Therefore, there is a need for a BGA package that provides enhanced structural stiffness and high thermal conductivity but is also capable of reducing high frequency signal noise and creating more stable power and ground voltage references.